The present invention relates to the field of video signal processing apparatus which regenerates and decodes video signals employing a programmable signal processor.
The specifications of broadcasting system for television signals are becoming increasingly diverse. At present, NTSC broadcasting systems via broadcast satellite and communications satellite, high definition television broadcasting, and digital television broadcasting are already in operation, in addition to existing terrestrial television broadcasting in NTSC color format (hereafter referred to as NTSC television broadcasting).
As the specifications of broadcasting systems continue to diversify, television sets require the corresponding ability to receive television signals broadcast via a range of broadcasting systems. In addition, as information processing devices such as personal computers become increasingly popular, display performance of so-called VGA-class (Video Graphics Array) resolution is required for home-use television sets.
Conventionally, television signals from different broadcasting systems are received and processed by switching field frequency, resolution, and number of horizontal scanning lines for each system, and this has resulted in larger and more complicated circuits.
For example, FIG. 6 shows a block diagram of a television set designed to receive both NTSC television composite video signals and MUSE television composite video signals.
NTSC television composite video signals are received as follows. A tuner selects a channel for NTSC television composite video signals. Signals are amplified by a VIF (Video Intermediate Frequency) amplifier and then detected by a detector to generate baseband NTSC TV composite video signals. Baseband NTSC TV composite video signals are input to an input terminal 72 in FIG. 6. A clamping circuit 82 adjusts the DC level of the baseband NTSC television composite video signals to an appropriate level, and an analog-to-digital converter 83 quantizes the resultant baseband NTSC television composite video signals and converts them to digital signals. Sampling frequency for quantization is phase-locked to the color subcarrier and has a four times (hereafter referred to as 4 fsc) higher frequency than the color subcarrier: approximately 14 MHz. Digitized baseband NTSC TV composite video signals are fed to a NTSC video signal decoder 76N.
On the other hand, a synchronizing signal regenerator 75 for NTSC TV composite video signals regenerates a clock signal xcfx8681, phase-locked to the color subcarrier, from quantized and digitized baseband NTSC TV composite video signals with a resonance circuit comprising a crystal resonator 102. The synchronizing signal regenerator 75 also detects synchronizing signal components of quantized and digitized NTSC composite video signals with the clock signal xcfx8681, regenerates horizontal synchronizing signals and vertical synchronizing signals, and generates the required pulse signals such as a clock signal xcfx8682 phase-locked to input horizontal synchronizing signals and a clamp pulse. The NTSC TV composite video signal decoder 76N decodes NTSC TV composite video signals through a luminance signal process and a chrominance signal process using a range of signals including clock signal xcfx8681, clock signal xcfx8682, and horizontal synchronizing signals.
The 2nd phase extended definition television standard (ED2) baseband composite video signal decoder 76E regenerates horizontal high-emphasis processing signals from ED2 composite video signals, in addition to decoding by 76N, using the clock signals xcfx8681, clock signals phased-locked to xcfx8681, and synchronizing signals. Video signals after the above processing are sampled by a clock signal xcfx8683 synchronized with the horizontal synchronizing pulse and vertical synchronizing pulse of the output circuit for synchronizing video signals with the horizontal synchronizing pulse and vertical synchronizing pulse of the output circuit. The clock signal xcfx8683 is generated from a resonance circuit comprising a crystal resonator 103, and is synchronized with the horizontal synchronizing pulse and vertical synchronizing pulse of the output circuit. For ED2 composite video signals, after the abovementioned processing, a vertical high-emphasis processing signal is regenerated using the clock signal xcfx8683 and a clock signal phase-locked to xcfx8683.
At this point, the luminance signal process in 76N and the luminance signal process in 76E can be combined to share a common circuit, as can the chrominance signal process in 76N and the chrominance signal process in 76E.
The method for decoding MUSE television composite video signals is as follows. A tuner selects a channel, and the VIF (video intermediate frequency) circuit amplifies the signals received. The detector detects the waveform and generates baseband MUSE television composite video signals. Baseband MUSE TV composite video signals are input to an input terminal 71. A clamping circuit 92 adjusts the DC level of baseband MUSE television composite video signals to appropriate level, and an analog-to-digital converter 93 quantizes baseband MUSE television composite video signals and converts them to digital composite video signals. A clock signal which is phase-locked to the horizontal phase standard signal and is about 16.2 MHz is used as sampling frequency for quantization. Digitized MUSE TV composite video signals are fed to a MUSE TV composite video signal decoder 74. The decoder 74 regenerates wide-band high definition video signals by approximately interpolating untransmitted signals of sampling points employing infield interpolation, inframe interpolation, or interframe interpolation.
A synchronizing signal regenerator 73 for MUSE television composite video signals regenerates horizontal phase standard signals, horizontal synchronizing signals, vertical phase standard signals, and vertical synchronizing signals from MUSE composite video signals. In addition, the synchronizing signal regenerator 73 regenerates a clock signal xcfx8691 required for operating the MUSE composite video signal decoder, from a resonance circuit comprising a crystal resonator 100, and generates a range of control signals for the input signal. Moreover, for MUSE composite video signals, video signals of horizontal scanning period are compressed to 11/12 for transmission, requiring the decoder to decompress them. For this purpose, a clock signal xcfx8693, phase-locked to the horizontal scanning pulse of the display apparatus, whose frequency is about 44 MHz, is generated from the resonance circuit comprising the crystal resonator 101. At the final stage of decoding process for MUSE composite video signals, decoded video signals are sampled by the clock signal xcfx8693 of about 44 MHz, and synchronized with the horizontal scanning pulse. The digital-to-analog converters 87 and 97 convert each of the outputs of the NTSC television composite video signal decoder 76N, the ED2 composite video signal decoder 76E, and the MUSE television composite video signal decoder 74 to analog signals. The switching circuit 80 selects and outputs signals. At the same time, the switching circuit 79 also selects and outputs synchronizing signals.
The present invention relates to a video signal processing apparatus for regenerating and decoding video signals employing programmable signal processors.
In general, an exclusive decoder, synchronizing regenerator, and clock generator are required for decoding input television video signals of each signal standard. This has resulted in larger circuits and also disadvantages in cost and productivity.
The object of the present invention is to provide solutions to the above disadvantages.
(1) The present invention relates to a video signal processing apparatus employing a synchronizing signal processor for separating and processing the synchronizing signal from the composite video signal, a clock signal generator for generating the clock signal phase-locked to the horizontal phase standard signal in the video signal, a first programmable signal processor for decoding the video signal, a storage means for storing the output signal of the first programmable signal processor, a generating and processing means of the output synchronizing pulse for generating and processing the synchronizing pulse so as to display the video signal on the display apparatus, a memory for storing multiple programs which are used for processing the video signal after the first decoding step by said first programmable signal processor at receiving the output signal from said storage, and a control means for selecting and reading out a suitable program from the memory where the multiple programs are stored.
The present invention enables one video display apparatus to process signals with different formats by overwriting an operating program of the programmable signal processor depending on the format of the input composite video signal, and thus provides cost-efficient video signal processing apparatus with higher productivity.
(2) The present invention also relates to a video signal processing apparatus employing a synchronizing signal separator for separating the synchronizing signal from the composite video signal, a clock signal generator for generating the clock signal phase-locked to the horizontal phase standard signal in said video signal, a first programmable signal processor for decoding said video signal, a storage means for storing the output signal of the first programmable signal processor, a generating and processing means of the synchronizing pulse for generating and processing the output synchronizing pulse so as to display the video signal on a display apparatus, and a control means for selecting and reading out a suitable program from the memory for processing the video signal after the first decoding step by said first programmable signal processor at receiving the output signal from said storage means.
The present invention enables one device to process signals of many different formats by switching programmable processors and clock signal generators depending on the format of the input composite video signal.
(3) The present invention also relates to a video signal decoder which generates a clock signal phase-locked to an external input synchronizing signal which is unlocked to a first composite video signal, and employs a first clock signal generator for phase-locking said clock signal to the synchronizing pulse xcfx8621 for displaying an image on a display apparatus. For displaying two video signals with different signal formats on the same screen, a first synchronizing signal is separated from a first composite video signal, and a clock signal for a second video composite signal is generated from an external synchronizing signal so as to generate a pulse for displaying a second video composite signal.
By reading out and displaying the first and second video signals stored in the memory after synchronizing them to the same clock signal, i.e., a clock signal phase-locked to the synchronizing pulse for displaying the video signal, an entire or a part of video signals with two different signal formats can be displayed on the same screen.
(4) The present invention also relates to a video signal decoder employing a clock signal generator for generating the clock signal phase-locked to the horizontal phase standard signal in the input composite video signal, another clock signal generator for generating the clock signal phase-locked to the synchronizing pulse for driving a display apparatus so as to display the video signal on the screen, and a Voltage Controlled Oscillator (VCO) which enables each clock signal generator to output different frequency signals. The VCO enables to output wideband frequency depending on the format of the input video signal.
(5) The present invention relates to a video signal processing apparatus comprising a CRT as an apparatus for displaying the composite video signal. The invention employs a second programmable signal processor for reading out the composite video signal stored in the memory with reference to the synchronizing signal generated from a synchronizing pulse generator for displaying decoded composite video signals, a memory which stores multiple programs for controlling said second programmable signal processor, and a control means for selecting and reading out a program stored in said memory depending on the format of the input video signal and writing in the selected program to a memory of the programmable processor. This enables the programmable processor to select required deflection process corresponding to the format of the video signal to be displayed with reference to the synchronizing pulse for displaying the video signal, and thus realizes one apparatus to handle multiple display formats.